The present invention concerns networking computing devices and pertains particularly to a flexible multi-frequency repeater.
For proper operation of a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) network it is necessary to limit the round-trip propagation delay of data between any two end nodes across the network. The goal is to insure that the largest packet fragment, as a result of a collision, seen on a collision domain is less than a minimum size packet. This is accomplished by fulfilling the requirements of Sections 4.2.3.2.3 and 4.4.2.1 of the ANSI/IEEE 802.3 standard and limiting the number of repeaters between any two data terminal equipment (DTE), such as an end station, a bridge, a router or a switch.
Essentially the ANSI/IEEE 802.3 standard allows for a round-trip propagation time of no more than 572 bit times. A bit time is equal to 100 nanoseconds for a 10 megabit network. The propagation of data across a network segment is measured in bit times. Various delay sources subtract from the overall delay budget. For example, media lengths, such as cable segments, introduce propagation delay. Repeaters introduce delay for start-up and steady state operation and interpacket gap shrinkage. Media Attachment Units (MAUs) introduce delay for start-up and steady state operation, and collision detect and de-assertion. There is also delay resulting from the end node response. For each of the these sources of delay, the ANSI/IEEE 802.3 standard specifies an allowable maximum delay.
Repeaters that conform to the ANSI/IEEE 802.3 and 802.3u Ethernet Carrier Sense Multiple Access with Collision Detection (CSMA/CD) standard are transparent to the nodes attached to them. These repeaters provide such basic functions as signal amplification, signal symmetry, signal timing, jitter reduction, preamble regeneration, collision handling, collision jam generation and electrical isolation.
Repeaters are commonly cascaded in a tree arrangement such that there is one upper repeater with a number of secondary repeaters below it. Below the secondary repeaters can exist additional levels of repeaters. For each level of repeater, two additional repeater delays are added between the nodes which may exist at the lowest level of the tree. Repeaters generally have a fixed number of ports. The limited number of ports combined with the maximum round trip delay requirement limits the number of end nodes that can exist in a given collision domain. This number can be increased by interconnecting repeaters via an inter-repeater bus (also called an inter-repeater backplane). The inter-repeater bus can be generally brought out external to each repeater to interconnect several repeaters. When repeaters are interconnected in this manner, they represent a network delay equivalent to a single repeater. Hence, fixed port count repeaters can be interconnected to increase the system port count, without increasing network delays between any two end nodes. Such a method of interconnection is generally referred to as "data stacking".
The inter-repeater bus (IRB) typically utilizes a signal set to interconnect repeaters in such a manner that one or more repeaters act as one large repeater. The signal set generally consists of data, control and clocking signals.
With increased port count comes increased bandwidth requirements. A method to increase the available bandwidth within data stacks is to employ multiple segments. A segment represents a collision domain. All nodes within a given segment compete for the bandwidth of that segment. With multi-segment repeaters, groups of ports can be assigned to different segments, thus dividing the bandwidth demand among the available segments.
Within multiple-segment repeaters, each segment is implemented using a separate inter-repeater bus. Data stacking and multi-segments are combined when multiple inter-repeater buses are used to interconnect repeaters. Any one port, or groups of ports, or all ports of a given repeater can be assigned and connected to any one inter-repeater bus from the available pool of inter-repeater buses. All the ports of a single segment repeater are said to be on the same segment. All devices attached to the ports of a single segment repeater share the finite bandwidth of that segment.
Repeater products are generally designed using repeater integrated circuits. Repeater integrated circuits generally provide all the functions necessary to provide basic repeater functionality as defined in Section 9 of the ANSI/IEEE Std. 802.3. Repeater integrated circuits provide a fixed limited number of repeater ports. In order to provide for larger port counts, repeater integrated circuit are interconnected using an inter-repeater bus, as discussed above. Also as discussed above, the inter-repeater bus typically utilizes a signal set to interconnect integrated circuit repeaters in such a manner that one or more integrated circuit repeaters act as one large repeater. The signal set generally consists of data, control and clocking signals.
The inter-repeater bus concept is widely used among 10 megabit 802.3 repeaters. This concept has been further extended to include multiple inter-repeater buses in a given product and/or in a data stack of several such products. With the shared nature of an 802.3 CSMA/CD network, as the number of ports increase on any given network segment, the available bandwidth to any given port effectively decreases. Separate inter-repeater buses can be used to create additional network segments. The bandwidth demand is then divided among the number of network segments. In order to implement multiple segments in this manner, several separate inter-repeater buses need to be implemented within a given repeater. For example, a product which supports up to four segments would require four internal inter-repeater buses. To support data stacking, the four internal inter-repeater buses also need to be brought external to the product.
An inter-repeater bus allows multiple repeater circuits to function as one logical repeater. Essentially there are three signal types associated with an inter-repeater bus: data, clocking and control. Actual network traffic is carried on the data signals. For 10 megabit operation a single data signal can be used when the data is transferred across the inter-repeater bus at 10 MHz.
Clocking signals are used to synchronously transfer data between devices attached to the inter-repeater bus. Control signals typically fall into two categories; collision and data. The data control signals control the path and flow of data between devices on local and stacked inter-repeater buses. The collision control signals are exchanged between devices on the local and stacked inter-repeater buses to signal when collisions occur on a given port, groups of ports, or on ports on different repeaters within a stack.
As discussed above, in order to minimize the delay through a repeater, the inter-repeater bus is generally implemented as a shared set of data signals. Each repeater integrated circuit attaches directly to the shared inter-repeater bus. Once the individual repeater integrated circuits are interconnected in this fashion they act as one large repeater with the same properties and functions as any one individual integrated circuit. All the ports of a repeater with one common inter-repeater bus are said to be on the same network segment. The inter-repeater bus can also be brought external to a repeater product such that several repeater products can be interconnected to form one large data stack, as discussed above.
With the emergence of 100 megabit CSMA/CD (802.3U) repeaters, a similar inter-repeater bus concept has also been applied. Hence, 100 megabit repeater integrated circuits can be interconnected via a 100 megabit version of the inter-repeater bus. For 100BaseT inter-repeater bus operation the number of data signals present is typically four, when 5 bit-to-4 bit decoding has occurred, otherwise 5 data signals exist.
It is also possible to integrate 10 megabit and 100 megabit repeater functions within the same repeater. This is done, for example, utilizing two inter-repeater buses: one 10 megabit inter-repeater bus and one 100 megabit inter-repeater bus. The speed of a given port is determined and that port is electrically interconnected to the appropriate inter-repeater bus, either the 10 megabit inter-repeater bus or the 100 megabit inter-repeater bus. The concept of multi-segments and multiple inter-repeater buses has similarly been extended to 100 megabit repeaters and repeater integrated circuits
When using combined 10 megabit and 100 megabit repeaters, typically users start with environments of 10 megabit and 100 megabit equipment which are interconnected via the repeater. However, it is anticipated that as all older 10 megabit network devices are upgraded with newer, high-speed 100 megabit devices there will come a point at which no ports of a 10/100 megabit repeater will use the 10 megabit capabilities of the repeater. Thus it is possible that all ports will reside on the 100 megabit inter-repeater bus. Hence, the 10 megabit inter-repeater bus will be unused and idle. This wastes the capacity and bandwidth of an inter-repeater bus.